How the CPU Runs Programs with the Fetch-Execute Cycle
Byte stands inside a glowing circuit board cityscape, holding a clipboard labeled 'Instructions' and pointing at a flashing memory bank while a tiny program marches step-by-step through illuminated pathways toward a central processor core humming with activity.
- Explain the three stages of the fetch-decode-execute cycle and the role of each stage in running a program.
- Identify the function of key CPU components — the Program Counter, Instruction Register, and ALU — during the cycle.
- Predict what happens to the Program Counter after each instruction is fetched.
- Compare how different types of instructions (arithmetic, load/store, branch) are handled during the execute stage.
- Describe why the fetch-decode-execute cycle is fundamental to running any program on any CPU.
Key terms
- Program Counter (PC)
- A register holding the memory address of the next instruction to fetch.
- Instruction Register (IR)
- A register that holds the instruction currently being decoded and executed.
- Control Unit
- The component that decodes instructions and generates signals directing the rest of the CPU.
- Arithmetic Logic Unit (ALU)
- The circuit that performs arithmetic and logical operations during execution.
- Pipelining
- Overlapping the fetch, decode, and execute stages of successive instructions to raise throughput.
The Roles of the Registers
Two registers drive the cycle. The Program Counter always names where the next instruction lives in memory, advancing automatically after each fetch so execution flows forward. The Instruction Register holds the fetched bits while the Control Unit decodes them into control signals. Branch instructions break the default flow by overwriting the Program Counter with a target address, which is exactly how loops and if-statements redirect execution. Understanding that the PC is a normal register you can overwrite, not a fixed counter, is the key to seeing how control flow works at the hardware level.
Pipelining Versus Simultaneity
A common confusion is that fast CPUs run all instructions at once. They do not. Each instruction still passes through fetch, decode, and execute in order. Pipelining improves throughput by overlapping stages of different instructions, so while one instruction executes, the next is decoded and the one after is fetched, like an assembly line. A classic non-pipelined CPU may need several clock cycles per instruction, while a pipelined CPU averages roughly one completed instruction per cycle. Speed comes from billions of clock pulses per second plus pipeline overlap, not from genuine simultaneity of a whole program.
Worked examples
Trace the cycle and Program Counter for an ADD instruction at address 0x00A4 in a RISC-style machine.
- Fetch: the CPU reads the 4-byte instruction at the address 0x00A4 held in the PC into the Instruction Register.
- Increment: the PC advances by 4 to 0x00A8, pointing at the next 4-byte instruction.
- Decode: the Control Unit interprets the bit pattern as ADD R1, R2.
- Execute: the ALU adds the values in R1 and R2 and stores the result, then the cycle restarts at 0x00A8.
Answer: After the ADD completes, the PC holds 0x00A8 and the sum sits in the destination register.
Activity
Arrange the CPU cycle steps in the correct order for a single instruction, then trace what happens to the Program Counter.
Practice
State the new Program Counter value after a branch instruction jumps to address 0x0050.
Describe what the Control Unit does during the decode stage of the cycle.
Common mistakes to avoid
- A CPU runs all instructions at onceEach instruction passes through the cycle in order; pipelining overlaps stages, not whole programs simultaneously.
- Each clock pulse is one full cycleA clock pulse is one tick; an instruction may take several ticks across its three stages.
Check your understanding
What is the primary purpose of the Program Counter (PC) register during the fetch-decode-execute cycle?
A student claims that a CPU executes all the instructions in a program simultaneously to run it faster. Which statement best refutes this claim?
During which stage of the fetch-decode-execute cycle does the Control Unit determine what operation an instruction requests?
A branch instruction in a program causes execution to jump from address 0x0020 to address 0x0050. What happens to the Program Counter during the execute stage of this instruction?
Recap
The fetch-decode-execute cycle fetches an instruction named by the Program Counter into the Instruction Register, decodes it in the Control Unit, and executes it via the ALU or memory. Branches overwrite the PC, and pipelining overlaps stages for throughput.
Reflect
How does seeing the Program Counter as an overwritable register change how you picture loops?